1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device including a memory device (SRAM: Static Random Access Memory) allowing random write and read.
2. Description of the Background Art
The SRAM have been known as a kind of semiconductor memory device. The SRAM has such advantages over a DRAM (Dynamic Random Access Memory) that refresh operation is not required and a storage state is stable.
FIG. 24 is an equivalent circuit diagram of an SRAM memory cell of a high resistance load type. Referring to FIG. 24, the memory cell includes a pair of high resistances R1 and R2 serving as a load and also includes a pair of driver transistors Q1 and Q2 as well as a pair of access transistors Q3 and Q4.
Each of paired high resistances R1 and R2 has one end connected to a V.sub.cc power supply 110 and the other end connected to a storage node N1 or N2.
Each of paired driver transistors Q1 and Q2 and paired access transistors Q3 and Q4 is formed of an MOS (metal Oxide Semiconductor) transistor. Each of paired driver transistors Q1 and Q2 has a source region connected to a GND (ground potential) 112. A drain region of driver transistor Q1 is connected to storage node N1, and the drain region of driver transistor Q2 is connected to storage node N2. A gate of driver transistor Q1 is connected to storage node N2, and a gate of driver transistor Q2 is connected to storage node N1.
One of a pair of source/drain regions of access transistor Q3 is connected to storage node N1, and the other of the source/drain regions is connected to a bit line 107. One of a pair of source/drain regions of access transistor Q4 is connected to storage node N2, and the other of the source/drain regions is connected to a bit line 108. Each of a gate of access transistors Q3 and Q4 is connected to a word line 109.
Now, a memory cell structure of the conventional SRAM of the high resistance load type will be described below.
FIGS. 25-28 are plans showing sections of the memory cell structure of the conventional SRAM at different levels in accordance with the order from a lowermost layer to an uppermost layer. More specifically, FIGS. 25 and 26 show structures of driver transistor pair Q1 and Q2 as well as access transistor pair Q3 and Q4. FIG. 27 shows a structure of high resistance pair R1 and R2, and FIG. 28 shows a structure of the bit lines.
Referring first to FIG. 25, driver transistor pair Q1 and Q2 as well as access transistor pair Q3 and Q4 are formed at a surface of a silicon substrate 301.
Driver transistor Q1 has a drain region 311b, a source region 311c, a gate insulating layer (not shown) and a gate electrode layer 325a. Drain region 311b and source region 311c are formed of n-type diffusion regions and are spaced from each other to define a channel region therebetween. Gate electrode layer 325a is opposed to the channel region with the gate insulating layer therebetween.
Driver transistor Q2 has a drain region 311d, a source region 311e, a gate insulating layer (not shown) and a gate electrode layer 325b. Drain region 311d and source region 311e are formed of n-type diffusion regions and are spaced from each other to define a channel region therebetween. Gate electrode layer 325b is opposed to the channel region with the gate insulating layer therebetween.
Access transistor Q3 has a pair of source/drain regions 311a and 311b, a gate insulating layer (not shown) and a gate electrode layer 315. Source/drain regions 311a and 311b are formed of n-type diffusion regions and are spaced from each other to define a channel region therebetween. Gate electrode 315 is opposed to the channel region with the gate insulating layer therebetween.
Access transistor Q4 has a pair of source/drain regions 321a and 321b, a gate insulating layer (not shown) and a gate electrode layer 315. Source/drain regions 321a and 321b are formed of n-type impurity diffusion regions and are spaced from each other to define a channel region therebetween. Gate electrode 315 is opposed to the channel region with the gate insulating layer therebetween.
Gate electrode layers 315 of access transistors Q3 and Q4 are formed of a single conductive layer, and are integral with the gate electrode layers of a pair of memory cells aligned laterally (i.e., in the row direction indicated by arrow X) to each other, forming the word line.
Drain region 311b of driver transistor Q1 and source/drain region 311b of access transistor Q3 are formed of a single n-type diffusion region. Source region 311c of driver transistor Q1 and source region 311e of driver transistor Q2 are connected together via an n-type impurity diffusion region 311f, and are formed of a single n-type diffusion region.
Gate electrode layer 325a of driver transistor Q1, gate electrode layer 325b of driver transistor Q2, gate electrode layers 315 of access transistors Q3 and Q4 are formed of composite films, each of which is made of polycrystalline silicon doped with impurity (will be referred to as "doped polycrystalline silicon" hereinafter) and high melting point silicide, and are formed of electrically conductive layers located at the same level. Isolating oxide films are formed at portions other than the n-type diffusion regions and channel regions.
Referring to FIG. 26, gate electrode layers 325a, 325b and 315 are covered with an insulating layer (not shown). This insulating layer is provided with contact holes 331h, 333h and 331i. Contact hole 331h reaches portions of gate electrode layer 325a and n-type diffusion region 321b. Contact hole 333h reaches portions of gate electrode layer 325b and n-type diffusion region 333. Contact holes 331h and 333h are so-called shared direct contact holes. Contact hole 331i reaches n-type diffusion region 311d.
A first doped polycrystalline silicon layer 331 is in contact with gate electrode layer 325a of n-type diffusion region 321b through contact hole 331h, and is also in contact with drain region 311d of driver transistor Q1 through contact hole 331i. A second doped polycrystalline silicon layer 333 is in contact with source/drain region 311b of access transistor Q3 and gate electrode layer 325b through contact hole 333h.
Referring to FIG. 27, first and second doped polycrystalline silicon layers 331 and 333 are covered with an insulating layer (not shown). This insulating layer is provided with apertures 341i and 341h which exposes portions of the surfaces of first and second doped polycrystalline silicon layers 331 and 333. There is also provided a resistance layer 341 made of polycrystalline silicon, which is in contact with second doped polycrystalline silicon layer 333 via aperture 341h and is in contact with first doped polycrystalline silicon layer 331 via aperture 341i.
Resistance layer 341 has regions 341a, 341c and 341e, which are doped with n-type impurity and will be referred to as "doped regions" hereinafter, and regions 341b and 341d which are not doped with impurity and will be referred to as "non-doped regions" hereinafter. Doped regions 341a and 341c are in contact with second and first doped polycrystalline silicon layers 333 and 331 via apertures 341h and 341i, respectively. Non-doped regions 341b and 341d extend in the same direction from doped regions 341a and 341c, respectively. Non-doped regions 341b and 341d have a high resistance value and form high resistances R1 and R2, respectively. Doped region 341e is connected to ends of non-doped regions 341b and 341d, and is utilized as a V.sub.cc interconnection of the memory cell.
Referring to FIG. 28, resistance layer 341 is covered with an insulating layer (not shown). This insulating layer is provided with contact holes 351h and 351i which reach portions of the surfaces of source/drain regions 311a and 321a of access transistors Q3 and Q4, respectively. Aluminum (Al) interconnection layers 351a and 351b are in contact with source/drain regions 311a and 321a through contact holes 351h and 351i, respectively. Aluminum interconnection layers 351a and 351b are used as bit lines.
The conventional memory cell structure shown in FIG. 25 is disclosed, for example, in TOMOHISA et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.SC-22, NO. 5, OCTOBER 1987, pp. 727-732.
The conventional SRAM has the memory cell structure described above. However, it is difficult to reduce (1) a longitudinal size and (2) a lateral size of the memory cell structure of the conventional SRAM, so that high integration of the structure is difficult. This will be described below in detail.